Artificial intelligence (AI) has become the linchpin in a growing number of products, services, and research programs which are aimed at automating and enhancing the human decision-making process. Indeed, AI is poised to play a critical role in the future of healthcare, transportation, manufacturing, and defense, to name a few. However, there are still several application domains (satellites, wearables, wireless, etc.) that cannot afford the size, weight, and power (SWaP) overheads associated with executing state-of-the-art AI algorithms. This talk will discuss previous and ongoing research to bridge the gap and enable AI in the most SWaP-constrained environments. This research takes a holistic approach, examining the entire AI stack, from devices and circuits to algorithms and applications.
At the lowest level, research on memristor-based circuits for implementing weighted communication pathways in artificial neural networks (ANNs) will be presented. Memristors reduce the power and latency associated with running ANNs on traditional computer architectures by directly emulating both the memory and computation of biological synapses. In addition, memristor plasticity enables on-chip learning and allows ANNs to function in the presence of hardware defects and process variations. Moving up the design hierarchy, research on ANN topologies with partially random connectivity, which can lead to reduced hardware overhead and training cost while achieving state-of-the-art performance on classification tasks, will be discussed. Research on stochastic representation of information, which can be leveraged to improve the size and performance of ANN circuits, will be presented. In conclusion, the talk will highlight some recent research related to the trustworthiness and potential security vulnerabilities of AI hardware.